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LTC1153 Auto-Reset Electronic Circuit Breaker
FEATURES
s s s s s s s s s s
DESCRIPTIO
Programmable Trip Delay: 15s to >100ms Programmable Trip Current: 1mA to >20A Programmbale Auto-Reset Time: 1ms to >10 sec. 4.5V to 18V Supply Range Drives Low RDS(ON) N-Channel MOSFETs Status Output Indicates Fault Condition Thermal Trip with PTC Thermistor 8A IQ in Standby Mode No External Charge Pump Capacitors Available in 8-Pin SOIC
The LTC1153 electronic circuit breaker drives a low cost N-channel MOSFET to interrupt power to a sensitive electronic load in the event of an over-current condition. The breaker remains tripped for a period of time set by an external timing capacitor and then is automatically reset. This cycle continues until the over-current condition is removed, protecting both the sensitive load and the MOSFET switch. The trip current, trip delay time and auto-reset period are programmable over a wide range to accommodate a variety of load impedances. An active high shutdown input is also provided and interfaces directly to a PTC thermistor for thermal circuit breaking. An open-drain output is provided to report breaker status to the P. The LTC1153 is available in both 8-pin DIP and 8-pin SOIC packages.
APPLICATI
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S
Power Bus Circuit Breaker SCSI Termination Power Protection Regulator Over-Current Protection Battery Short-Circuit Protection DC Motor Stall Protection Sensitive System Power Interrupt
TYPICAL APPLICATI
5V/1A Electronic Circuit Breaker with 1ms Trip Delay, 200ms Auto-Reset Period and 70C Thermal Shutdown
10 ON/OFF CT 0.22F Z5U TO P 51k GND 5V **70C PTC SENSITIVE 5V LOAD SHUTDOWN IN CT LTC1153 STATUS G 51k IRLR024 VS CD RD 0.01F 100k DS
TRIP DELAY (ms)
*RSEN 0.1 1
0.1
ALL COMPONENTS SHOWN ARE SURFACE MOUNT. * IMS026 INTERNATIONAL MANUFACTURING SERVICE, INC. (401) 683-9700 ** RL2006-100-70-30-PT1 KEYSTONE CARBON COMPANY (814) 781-1591
LTC1153 * TA01
0.01 1 10 CIRCUIT BREAKER CURRENT (A) 100
U
Trip Delay Time
RSEN = 0.1 RD = 100k CD = 0.01F
LTC1153 * TA02
UO
UO
1
LTC1153 ABSOLUTE AXI U RATI GS
Current (Any Pin).................................................. 50mA Operating Temperature LTC1153C .............................................. 0C to 70C Storage Temperature Range ................. - 65c to 150C Lead Temperature (Soldering, 10 sec.)................ 300C
Supply Voltage ........................................................ 22V Input Voltage ..................... (VS + 0.3V) to (GND - 0.3V) Timing Capacitor Voltage ... (VS + 0.3V) to (GND - 0.3V) Gate Voltage ....................... (VS + 24V) to (GND - 0.3V) Status Output Voltage .............................................. 15V
PACKAGE/ORDER I FOR ATIO
TOP VIEW IN 1 TIMING CAP 2 STATUS 3 GND 4 8 7 6 5 VS DRAIN SENSE GATE SHUTDOWN
ORDER PART NUMBER LTC1153CN8
N8 PACKAGE 8-LEAD PLASTIC DIP
LTC1153 * PO01
TJMAX = 100C, JA = 130C/W (N8)
ELECTRICAL CHARACTERISTICS VS = 4.5V to 18V, TA = 25C, CT = 0.1F, VSD = 0V unless otherwise noted.
SYMBOL VS IQ IQ IQ VINH VINL IIN CIN VCT ICT VSDH VSDL ISD VSEN ISEN PARAMETER Supply Voltage Quiescent Current OFF Quiescent Current ON Quiescent Current ON Input High Voltage Input Low Voltage Input Current Input Capacitance Timing Capacitor Threshold Voltage Timing Capacitor Current Shutdown Input High Voltage Shutdown Input Low Voltage Shutdown Input Current Drain Sense Threshold Voltage
q
CONDITIONS
q
VS = 5V, VIN = 0V VS = 5V, VIN = 5V VS =12V, VIN = 5V
q q
0V < VIN < VS VS = 5V VS = 12V VS = 12V
0V < VIN < VS
Drain Sense Input Current
0V < VSEN < VS
2
U
U
W
WW
U
W
TOP VIEW IN 1 TIMING CAP 2 STATUS 3 GND 4 8 7 6 5 VS DRAIN SENSE GATE SHUTDOWN
ORDER PART NUMBER LTC1153CS8
S8 PACKAGE 8-LEAD PLASTIC SOIC
LTC1154 * PO02
S8 PART MARKING 1153
TJMAX = 100C, JA = 150C/W
MIN 4.5
LTC1153C TYP 8 85 180
MAX 18 20 120 400 0.8 1
UNITS V A A A V V A pF V V A V V A mV mV A
2
q
5 2.1 2.0 3.0
q q q
2.5 2.6 4.2
2.9 3.2 6.0 0.8 1
2
80 75
100 100
120 125 0.1
q
LTC1153 ELECTRICAL CHARACTERISTICS VS = 4.5V to 18V, TA = 25C, CT = 0.1F, VSD = 0V unless otherwise noted.
SYMBOL PARAMETER CONDITIONS VS = 5V VS = 6V VS = 12V ISTAT = 400A VSTAT = 12V VS = 5V, CGATE = 1000pF Time for VGATE > VS + 2V Time for VGATE > VS + 5V VS = 12V, CGATE = 1000pF Time for VGATE > VS + 5V Time for VGATE > VS + 10V tOFF Turn-OFF Time VS = 5V, CGATE = 1000pF Time for VGATE < 1V VS = 12V, CGATE = 1000pF Time for VGATE < 1V tTD Minimum Trip Delay VS = 5V, CGATE = 1000pF Time for VGATE < 1V VS = 12V, CGATE = 1000pF Time for VGATE < 1V tSD Shutdown Turn-OFF Time VS = 5V, CGATE = 1000pF Time for VGATE < 1V VS = 12V, CGATE = 1000pF Time for VGATE < 1V The q denotes specifications which apply over the operating temperature range.
q q q q q
MIN 6.0 7.5 15.0
LTC1153C TYP 7.0 8.3 18.0 0.05
MAX 9.0 15.0 25.0 0.4 1
UNITS V V V V A s s s s s s s s s s
VGATE - VS Gate Voltage Above Supply
VSTAT ISTAT tON
Status Output Low Voltage Status Output Leakage Current Turn-ON Time
30 100 20 50 10 10 5 5
110 450 80 160 36 28 25 23 17 13
300 1000 200 500 60 60 40 40 40 35
TYPICAL PERFOR A CE CHARACTERISTICS
Standby Supply Current
50 45 40
SUPPLY CURRENT (A)
VIN = 0V TA = 25C
SUPPLY CURRENT (A)
35 30 25 20 15 10 5 0 0 5 10 15 SUPPLY VOLTAGE (V) 20
LTC1153 * TPC01
600 500 400 300 200 100 0 0 5 10 15 SUPPLY VOLTAGE (V) 20
LTC1153 * TPC02
VGATE - VS (V)
UW
Supply Current ON
1000 900 800 700 TA = 25C 24 22 20 18 16 14 12 10 8 6 4
MOSFET Switch Gate Voltage
0
5
10 15 SUPPLY VOLTAGE (V)
20
LTC1153 * TPC03
3
LTC1153
TYPICAL PERFOR A CE CHARACTERISTICS
Input Threshold Voltage
2.4 2.2
INPUT THRESHOLD VOLTAGE (V)
DRAIN SENSE THRESHOLD VOLTAGE (mV)
2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0 5 10 15 SUPPLY VOLTAGE (V) 20
LTC1153 * TPC04
120 110 100 90 80 70 60 50 0 5 10 15 SUPPLY VOLTAGE (V) 20
LTC1153 * TPC05
RESET PERIOD (SEC)
VON VOFF
MOSFET Gate Turn-ON Time
1000 900 800 CGATE = 1000pF
50 45 40
TURN OFF TIME (s)
TURN ON TIME (s)
700 600 500 400 300 200 100 0 0 5 10 15 SUPPLY VOLTAGE (V) 20
LTC1153 * TPC07
30 25 20 15 10 5 0 0 5 10 15 SUPPLY VOLTAGE (V) 20
LTC1153 * TPC08
TRIP TIME (s)
VGS = 5V
VGS = 2V
Standby Supply Current
50 45 40 VIN = 0V
800
SUPPLY CURRENT (A)
INPUT THRESHOLD VOLTAGE (V)
SUPPLY CURRENT (A)
35 30 25 20 15 10 5 0 -50 -25 VS = 18V VS = 5V 50 25 0 75 TEMPERATURE (C) 100 125
4
UW
LTC1153 * TPC10
Drain Sense Threshold Voltage
150 140 130
Auto-Reset Period
10 TA = 25C 3.3F 1 1F 0.33F 0.1 0.1F 0.033F 0.01 0 5 10 15 20 SUPPLY VOLTAGE (V)
LTC1153 * TPC06
MOSFET Gate Turn-OFF Time
50
CGATE = 1000pF TIME FOR VGATE < 1V
Built-In Trip Delay
45 40 35 30 25 20 15 10 5 0 0 5 10 15 SUPPLY VOLTAGE (V) 20
LTC1153 * TPC09
CGATE = 1000pF TIME FOR VGATE < 1V VSEN = VS - 1V NO EXTERNAL DELAY
35
Supply Current ON
1000 900 VIN = 5V 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.O 0.8 0.6 100 125
Input ON Threshold Voltage
700 600 500 400 300 200 100 VS = 5V VS = 12V
VS = 5V VS = 18V
0 -50 -25
50 25 0 75 TEMPERATURE (C)
0.4 -50 -25
50 25 0 75 TEMPERATURE (C)
100
125
LTC1153 * TPC11
LTC1153 * TPC12
LTC1153
TYPICAL PERFOR A CE CHARACTERISTICS
Shutdown Threshold Voltage
2.4
10 *SECONDS OF DELAY PER F CT
SHUTDOWN THRESHOLD VOLTAGE (V)
2.2 2.0 1.8 1.6 1.4 1.2 1.O 0.8 0.6 0.4 -50 -25 50 25 0 75 TEMPERATURE (C) 100 125 VS = 5V VS = 18V
AUTO-RESET TIME (s/F)
GATE DRIVE CURRENT (A)
PI FU CTIO S
Input and Shutdown Pins The LTC1153 input pin is active high and activates all of the protection and charge pump circuitry when switched ON. The shutdown pin is designed to break the circuit if a secondary fault condition (over temperature, etc.) is detected. The LTC1153 logic and shutdown inputs are high impedance CMOS gates with ESD protection diodes to ground and supply and therefore should not be forced beyond the power supply rails. The shutdown pin should be connected to ground when not in use. Timing Capacitor Pin (Auto-Reset Timer) The small capacitor charging current (4.2A) produces large delays with relatively small valued capacitors, but care must be taken to ensure that this current is not shunted to ground through a leaky capacitor or printed circuit board trace. The timing capacitor voltage is sensed by a high impedance CMOS comparator input with ESD clamp diodes to ground and supply and therefore should not be forced beyond the power supply rails. This pin can be grounded if the auto-reset function is not used. MOSFET Gate Drive Pin The MOSFET gate drive pin is either driven to ground when the switch is turned OFF or driven above the supply rail when the switch is turned ON. This pin is a relatively high impedance when driven above the rail (the equivalent of a few hundred k). Care should be taken to minimize any loading of this pin by parasitic resistance to ground or supply. Supply Pin The supply pin of the LTC1153 serves two vital purposes. The first is obvious: it powers the input, gate drive, regulation and protection circuitry. The second purpose is less obvious: it provides a Kelvin connection to the top of the drain sense resistor for the internal 100mV reference. The LTC1153 is designed to be continuously powered so that the gate of the MOSFET is actively driven at all times. If it is necessary to remove power from the supply pin and then re-apply it, the input pin (or enable pin) should be cycled a few milliseconds after the power is re-applied to reset the input latch and protection circuitry. Also, the input and enable pins should be isolated with 10k resistors to limit the current flowing through the ESD protection diodes to the supply pin.
UW
LTC1153 * TPC13
Auto-Reset Time*
1000
MOSFET Gate Drive Current
TA = 25C 100 VS = 18V VS = 12V 10
VS = 12V 1 VS = 5V VS = 18V
1
VS = 5V
0.1 -50
0.1
-25 0 50 75 25 TEMPERATURE (C) 100 125
0
4 8 12 16 GATE VOLTAGE ABOVE SUPPLY (V)
20
LTC1153 * TPC14
LTC1153 * TPC15
U
U
U
The supply pin of the LTC1153 should never be forced below ground as this may result in permanent damage to the device. A 300 resistor should be inserted in series with the ground pin if negative supply voltage transients are anticipated.
5
LTC1153
PI FU CTIO S
Drain Sense Pin The drain sense pin is compared against the supply pin voltage. If the voltage at this pin is more than 100mV below the supply pin, the input latch will trip and the MOSFET switch will be turned off. This pin is also a high impedance CMOS gate with ESD protection and therefore should not be forced beyond the power supply rails. Some loads, such as large supply capacitor, lamps, or motors require high inrush currents. An RC time is added between the sense resistor and the drain sense pin to ensure that the drain sense circuitry does not false trigger during start-up. This trip delay can be set from a few microseconds to many seconds. However, very long delays may put the MOSFET switch in risk of being destroyed by a short-circuit condition. (see Applications Information Section). Status Pin The status pin is an open-drain output which is driven low whenever the breaker is tripped. A 51k pull-up resistor should be connected between this output and a logic supply. The status pins of multiple LTC1153s can be OR'd together if independent fault sensing is not required. No connection is required to this pin when not in use.
BLOCK DIAGRA
VS LOW STANDBY CURRENT REGULATOR COMP 100mV REFERENCE 10s DELAY SHUTDOWN TTL-TO-CMOS CONVERTER SHUTDOWN
INPUT
TTL-TO-CMOS CONVERTER
GND
TIMER CAP STATUS
AUTO-RESET TIMER
6
W
U
U
U
ANALOG SECTION
DRAIN SENSE
GATE CHARGE AND DISCHARGE CONTROL LOGIC ANALOG DIGITAL R VOLTAGE REGULATORS INPUT LATCH ONE SHOT S OSCILLATOR AND CHARGE PUMP FAST/SLOW GATE CHARGE LOGIC
GATE
FAULT DETECTION AND STATUS OUTPUT DRIVER
LTC1153 * BD01
LTC1153 TEST CIRCUITS
5V INPUT 51k 1 IN CT LTC1153 STATUS GND G SD 6 5 VS DS 8 CP 0.01F RD100k IRLZ24 OUTPUT S1 SHUTDOWN 10 1
LTC1153 * TC01
TI I G DIAGRA
OFF NORMAL
RSEN 0.05
OVER-CURRENT (AUTO-CURRENT)
INPUT *200s OUTPUT
2 0.1F Z5U 3 4
7
STATUS
STATUS TIMING CAP SHUTDOWN *90ms
S1 CLOSED
*TIMES FOR COMPONENTS SHOWN IN TEST CIRCUIT
LTC1153 OPERATIO
The LTC1153 is an electronic circuit breaker with built-in MOSFET gate charge pump, over-current detection and auto-reset circuitry. The LTC1153 consists of the following functional blocks: TTL and CMOS Compatible Inputs The LTC1153 input and shutdown input have been designed to accommodate a wide range of logic families. Both input thresholds are set at about 1.3V with approximately 100mV of hysteresis. A low standby current voltage regulator provides continuous bias for the TTL-to-CMOS converter. The TTL-toCMOS converter output enables the rest of the circuitry. In this way the power consumption is kept to a minimum in the standby mode. Auto-Reset Timer An external timing capacitor, CT, is ramped up by a small current whenever a fault is detected, i.e., the switch latched off. When the timing capacitor ramps up to approximately 2.5V, the switch is turned back on and the timing capacitor discharged. If the circuit breaker output is still in an overload state, the breaker will latch off and this cycle will continue until the fault condition is removed.
Internal Voltage Regulation The output of the TTL-to-CMOS converter drives two regulated supplies which power the low voltage CMOS logic and analog blocks. The regulator outputs are isolated from each other so that the noise generated by the charge pump logic is not coupled into the 100mV reference or the analog comparator. Gate Charge Pump Gate drive for the MOSFET switch is produced by an adaptive charge pump circuit which generates a gate voltage substantially higher than the power supply voltage. The charge pump capacitors are included on-chip and therefore no external components are required to generate the gate drive. Drain Current Sense The LTC1153 is configured to sense the current flowing into the drain of an N-channel MOSFET switch. An internal 100mV reference is compared to the drop across a sense resistor (typically 0.002 to 0.10) in series with the drain lead. If the drop across this resistor exceeds the internal 100mV threshold, the input latch is reset and the gate is quickly discharged via a relatively large N-channel transistor.
W
NORMAL SHUTDOWN OFF
LTC1153 * TD01
UW
S1 OPEN
U
7
LTC1153
LTC1153 OPERATIO U
Status Output Driver The status circuitry continuously monitors the input and the gate charge control logic. The open-drain output is driven low when the input is turned ON and the breaker is latched off. The status circuitry is reset along with the input latch when the auto-reset circuitry retries the breaker or the input is cycled low.
Controlled Gate Rise and Fall Times When the input is switched ON and OFF, the gate is charged by the internal charge pump and discharged in a controlled manner. The charge and discharge rates have been set to minimize RFI and EMI emissions in normal operation. If a short-circuit or current overload condition is encountered, the gate is discharged very quickly (typically a few microseconds) by a large N-channel transistor.
APPLICATI
S I FOR ATIO
MOSFET and Load Protection The LTC1153 protects the power MOSFET switch by removing drive from the gate as soon as an over-current condition is detected and breaking the circuit to the load. Resistive and inductive loads can be protected with no external time delay in series with the drain sense pin. High inrush current loads, however, require that the trip delay time be set long enough to start the load but short enough to ensure the safety of the MOSFET. Resistive Loads
IN CT LTC1153 STATUS GND
Loads that are primarily resistive should be protected with as short a delay as possible to minimize the amount of time that the MOSFET switch or the load is subjected to an overload condition. The drain sense circuitry has a builtin trip delay of approximately 10s to eliminate false triggering by power supply or load transient conditions. This delay is sufficient to "mask" short load current transients and the starting of a small capacitor (<1F) in parallel with the load. The drain sense pin can therefore be connected directly to the drain current sense resistor as shown in Figure 1. Inductive Loads Loads that are primarily inductive, such as relays, solenoids and stepper motor windings should be protected with as short a delay as possible to minimize the amount of time that the MOSFET is subjected to an overload condition. The built-in 10s trip delay will ensure that the breaker is not false-tripped by a supply or load transient. No external delay components are required as shown in Figure 2.
8
U
12V VS DS G 15V SD
W
U
UO
+
100F 0.036
CT 0.22F
IRFZ24
CLOAD 1F
RLOAD 12
LTC1153 * F01
Figure 1. Protecting Resistive Loads
12V IN CT LTC1153 STATUS GND G 15V SD IRFZ24 VS DS
+
100F 0.036
CT 0.22F
1N5400
12V, 1A SOLENOID
LTC1153 * F02
Figure 2. Protecting Inductive Loads
Large inductive loads (>0.1mH) may require diodes connected directly across the inductor to safely divert the stored energy to ground. Many inductive loads have these diodes included. If not, a diode of the proper current rating
LTC1153
APPLICATI S I FOR ATIO U
Using the values shown in Figure 3, the start-up current is less than 100mA and does not false-trip the breaker. Lamp Loads The inrush current created by a lamp during turn-on can be 10 to 20 times greater than the rated operating current. The circuit shown in Figure 4 shifts the trip threshold up by a factor of 11:1 (to 30A) for 100ms while the bulb is turned on. The trip threshold then drops down to 2.7A after the inrush current has subsided.
12V
should be connected across the load, as shown in Figure 2, to safely divert the stored energy. Capacitive Loads Large capacitive loads, such as complex electrical systems with large bypass capacitors, should be powered using the circuit shown in Figure 3. The gate drive to the power MOSFET switch is passed through an RC delay network, R1 and C1, which greatly reduces the turn on ramp rate of the switch. And since the MOSFET source voltage follows the gate voltage, the load is powered smoothly and slowly from ground. This dramatically reduces the start-up current flowing into the supply capacitor/s which, in turn, reduces supply transients and allows for slower activation of sensitive electrical loads. (Diode, D1, provides a direct path for the LTC1153 protection circuitry to quickly discharge the gate).
12V IN CT LTC1153 STATUS GND G SD C1 0.33F 15V VS CD 0.01F DS CT 0.47F D1 1N4148 R1 1OOk R2 1OOk MTP3055E OUT RD 1OOk
+
470F 0.036
Figure 3. Powering Large Capacitive Loads
10
The RC network, RD and CD, in series with the drain sense input should be set to trip based on the expected characteristics of the load after start-up. With this circuit, it is possible to power a large capacitive load and still react quickly (10s) to break the circuit if a short-circuit condition is encountered. The ramp rate at the output of the switch as it lifts off ground is approximately: dV/dt = (VGATE - VTH)/(R1 x C1) And therefore the current flowing into the capacitor during start-up is approximately: ISTART-UP = CLOAD x dV/dt
TRIP DELAY TIME (1 = RC)
W
U
UO
+
470F IN CT LTC1153 STATUS GND G 1M SD 9.1V 12V/1A BULB
LTC1153 * F04
VS DS
10k 100k
0.036
CT 0.33F
VN2222LL 0.1F MTP3055EL
Figure 4. Lamp Driver with Delayed Protection
Selecting RD and CD Figure 5 is a graph of normalized breaker trip time versus breaker current. This graph is used to select the two delay components, RD and CD, which make up a simple RC delay between the drain sense resistor and the drain sense input.
+
CLOAD 100F
LTC1153 * F03
1
0.1
0.01 1 10 100 BREAKER CURRENT (1 = SET CURRENT)
LTC1153 * F05
Figure 5. Trip Delay Time vs Breaker Current
9
LTC1153
APPLICATI
S I FOR ATIO
The Y axis of the graph is normalized to one RC time constant. The X axis is normalized to the set current. (The set current is defined as the current required to develop 100mV across the drain sense resistor). Note that the trip delay time is shorter for increasing levels of MOSFET current. This ensures that the total energy dissipated by the MOSFET is always within the bounds established by the manufacturer for safe operation. (See MOSFET data sheet for further S.O.A. information). Using a Speed-Up Diode Another way to reduce the trip delay time is to "bypass" the delay resistor with a small signal diode as shown in Figure 6. The diode will engage when the drop across the drain sense resistor exceeds about 0.7V, providing a direct path to the sense pin and dramatically reducing the trip delay time. The drain sense resistor value is selected to limit the maximum DC breaker current to 4A.
12V IN CT LTC1153 STATUS GND G 15V SD LOAD IRF530 VS 0.01F DS CT 0.22F
+
100F 1N4148 1OOk 0.036
Figure 6. Using a Speed-Up Diode
Reverse Battery Protection The LTC1153 can be protected against reverse battery conditions by connecting a resistor in series with the ground lead as shown in Figure 7. The resistor limits the supply current to less than 50mA with -12V applied. Since the LTC1153 draws very little current while in normal operation, the drop across the ground resistor is minimal. the 5V P (or control logic) is protected by the 10k resistors in series with the input and status pins.
1F
10
U
12V 5V 120k 10k 5V P OR CONTROL LOGIC
W
U
UO
+
10F IN CT 0.47F CT 10k LTC1153 STATUS GND 300 G 15V SD 10k LOAD MTP12N06 DS VS 0.05
LTC1153 * F07
Figure 7. Reverse Battery Protection
Current Limited Power Supplies The LTC1153 requires at least 3.5V at the supply pin to ensure proper operation. It is therefore necessary that the supply to the LTC1153 be held higher than 3.5V at all times, even when the output of the switch is short circuited to ground. The output voltage of a current limited regulator may drop very quickly during short-circuit and pull the supply pin of the LTC1153 below 3.5V before the shutdown circuitry has had time to respond and remove drive from the gate of the power MOSFET. A supply filter should be added as shown in Figure 8 which holds the supply pin of the LTC1153 high long enough for the over-current shutdown circuitry to respond and fully discharge the gate, i.e., break the circuit.
>7V
LTC1153 * F06
+
100F
5V/2A REGULATOR *20
+
10F 0.1
+
IN CT LTC1153 STATUS GND G SD VS 0.1F DS *47F
1N4148 100k
IRLR024 SHORT CIRCUIT
*SUPPLY FILTER COMPONENTS
LTC1153 * F08
Figure 8. Supply Filter for Current Limited Supplies
LTC1153
APPLICATI S I FOR ATIO
Five volt linear regulators with small output capacitors are the most difficult to protect as they can "switch" from a voltage mode to a current limited mode very quickly. The large output capacitors on many switching regulators, on the other hand, may be able to hold the supply pin of the LTC1153 above 3.5V sufficiently long that this extra filtering is not required.
TYPICAL APPLICATIO S
Over-Temperature Circuit Breaker
12V IN 51k 0.47F CT LTC1153 STATUS GND G 30k SD *PTC THERMISTOR (100C) *RL3006-50-100-25-PT0 KEYSTONE 12V LOAD VS DS 5V MTD3055E
+
100F
5V
24V to 28V Over-Temperature Circuit Breaker
24V TO 28V
+
100F 3k
5V 51k 0.47F
IN CT LTC1153 STATUS GND
VS DS G
+
18V 10F
30k SD *PTC THERMISTOR (100C) *KEYSTONE RL2006-100-100-30-PT. MOUNT ON MOSFET OR LOAD HEAT SINK. 5V 24V TO 28V LOAD
U
Because the LTC1153 is micropower in both the standby and ON state, the voltage drop across the supply filter is less than 2mV, and does not significantly alter the accuracy of the 100mV drain sense threshold voltage.
Over-Voltage Circuit Breaker
4.75V TO 5.25V IN 5V 51k 0.22F CT LTC1153 STATUS GND G SD 5V LOAD SWITCH IS SHUTDOWN WHEN VS > 5.7V VS 100 DS 5.6V IRLD024
W
U
U
UO
+
10F
LTC1153 * TA03
LTC1153 * TA05
24V to 28V Over-Temperature Circuit Breaker with Bootstrapped Supply
24V TO 28V
+
100F 100k
IN 5V 51k 0.47F
MTP12N06
VS DS LTC1153 G
+
18V 10F 6.2k
CT STATUS GND
1N4148 MTP15N06E 30k 5V *PTC THERMISTOR (100C) 24V TO 28V LOAD
SD
LTC1153 * TA04
* KEYSTONE RL2006-100-100-30-PT. MOUNT ON MOSFET OR LOAD HEAT SINK. ** BOOTSTRAPPING REDUCES IQ(OFF) TO 60A, IQ(ON) = 1mA.
LTC1153 * TA06
11
LTC1153
TYPICAL APPLICATI
12V
12V Lamp Driver/Circuit Breaker with Auto-Reset
IN 5V CT 0.33F LTC1153 STATUS GND
VS DS
G 1M SD
5V
ON/OFF 51k
0.47F Z5U STATUS
Logic Controlled Battery Switch with Reverse Battery Protection, Ramped Turn-On and 10A Standby Current
Si9956DY 0.05
+
4 TO 6 CELLS ON/OFF 51k CT 0.47F STATUS LTC1153 STATUS GND G 0.22F SD DS IN VS 1N4148 100k 100k
300
12
UO
10k
S
Relay Driver with Over-Current Protection and Status Feedback
12V
+
470F 0.02 100k
5V
+
100F 2 IN VS 0.01F CT DS LTC1153 STATUS G 15V GND SD 1N4001 MTD3055E TO 12V LOAD 10k 1N4148 0.02
VN2222LL 0.1F IRFZ34 12V 12V/2A BULB
LTC1153 * TA07
1F
COIL CURRENT LIMITED TO 350mA CONTACT CURRENT LIMITED TO 5A
LTC1153 * TA08
SCSI Termination Power 1A Circuit Breaker with Auto-Reset and Ramped Turn-On
0.1 MTD3055EL 1N5817
+
100F 20 10k 1N4148
+
10F
4.25V/1A
+
IN CT LTC1153 STATUS GND G 0.22F SD
LTC1153 * TA09
VS 0.1F DS
47F 1N4148 100k 100k
+
SWITCHED BATTERY 47F/16V
LTC1153 * TA10
LTC1153
TYPICAL APPLICATI UO
470F VS 0.22F CT 0.47F Z5U STATUS LTC1153 STATUS GND G SD 0.22F DS 1N4148 100k 100k 1k 1F
LTC1153 * TA12
S
"4 Cell-to-5V" Regulator with 2A Current Limit, Auto-Reset, Ramped Turn-On and 10A Standby Current
+
4-CELL BATTERY PACK ON/OFF 51k CT 0.47F STATUS LTC1153 STATUS GND G 0.22F SD DS IN VS 1N4148 200pF 100k 100k 10k 8 7 1 3 LT1431 6 5 4 5V/1A IRLR024
+
100F 0.05
+
470F ESR < 0.5
LTC1153 * TA11
12V Step-Up Regulator with Soft Start, Auto-Reset Circuit Breaker (Pre-Regulator), Status Feedback and 10A Standby Current
0.02 5V IRLZ24 5 150F 47F VSW 4 LT1070 2 FB VC GND 3 1 VIN 10.72k 1% 50H 1N5820 12V/1A 330F
+
20 100k 1N4148
+ + +
ON/OFF 51k
IN
1.24k 1%
12V Step-Up Regulator with 1A Circuit Breaker (Post Regulator), Breaker Status Feedback and Ramped Output
50H 5V 1N5820 (12V)
+
150F 5 VSW 4 LT1070 2 FB VC GND 3 1 1k 1F VIN 10.72k 1%
+
330F 1N4148 IN 51k 1.24k 1% STATUS CT 0.47F Z5U LTC1153 STATUS GND G 12V SD 0.22F DS VS 0.1F 1N4148 100k 100k IRF530 10k 0.1
ON/OFF
+
12V/1A 47F 16V
LTC1153 * TA13
13
LTC1153
TYPICAL APPLICATI UO
5 12 7 100k 14 51k 10k 2N2907 240 MOTOR FAULT LED 0.33F
S
Auto-Reset Circuit Breaker with Programmable (1-6) Number of Retries Using Binary Counter
5V TO 18 V
+
100F 0.1
ON/OFF 5V 11 LOAD 74C193 4 16 VCC UP CARRY QD ABCDGND 15 1 10 9 INPUTS* *SET WITH 3-BIT BINARY WORD = 7 - N 8
IN CT 0.47F Z5U LTC1153 STATUS GND
VS DS G 12V SD 0.22F 1N4148 100k 100k IRF530
+
OUTPUT 47F
FAULT
LTC1153 * TA14
DC Motor Driver with Stall-Current Circuit Breaking (Auto-Reset), Thermal Overload Shutdown and 10A Standby Current
12V
+
470F 0.02
5V
ON/OFF
IN CT LTC1153 STATUS GND
VS 0.1F DS G 120k SD *PTC THERMISTOR (100C) 12V 100k
IRFZ34
M
1N5400
*RL3006-50-100-25-PTO KEYSTONE MOUNT ON MOTOR CHASIS OR MOSFET HEAT SINK
LTC1153 * TA15
14
LTC1153
PACKAGE DESCRIPTIO U
N8 Package 8-Lead Plastic Lead
0.400 (10.160) MAX 8 7 6 5 0.045 - 0.065 (1.143 - 1.651) 0.130 0.005 (3.302 0.127) 0.250 0.010 (6.350 0.254) 0.125 (3.175) MIN 0.020 (0.508) MIN 1 2 3 4 0.018 0.003 (0.457 0.076)
N8 0392
0.300 - 0.320 (7.620 - 8.128)
0.009 - 0.015 (0.229 - 0.381)
0.065 (1.651) TYP
(
+0.025 0.325 -0.015 +0.635 8.255 -0.381
)
0.045 0.015 (1.143 0.381) 0.100 0.010 (2.540 0.254)
S8 Package 8-Lead Plastic SOIC
0.189 - 0.197 (4.801 - 5.004) 0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0.016 - 0.050 0.406 - 1.270 0.053 - 0.069 (1.346 - 1.752) 0.004 - 0.010 (0.101 - 0.254) 0.228 - 0.244 (5.791 - 6.197) 0.150 - 0.157 (3.810 - 3.988) 8 7 6 5
0- 8 TYP
0.014 - 0.019 (0.355 - 0.483)
0.050 (1.270) BSC
1
2
3
4
SO8 0392
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of circuits as described herein will not infringe on existing patent rights.
15
LTC1153
U.S. Area Sales Offices
NORTHEAST REGION Linear Technology Corporation One Oxford Valley 2300 E. Lincoln Hwy.,Suite 306 Langhorne, PA 19047 Phone: (215) 757-8578 FAX: (215) 757-5631 SOUTHEAST REGION Linear Technology Corporation 17060 Dallas Parkway Suite 208 Dallas, TX 75248 Phone: (214) 733-3071 FAX: (214) 380-5138 CENTRAL REGION Linear Technology Corporation Chesapeake Square 229 Mitchell Court, Suite A-25 Addison, IL 60101 Phone: (708) 620-6910 FAX: (708) 620-6977 SOUTHWEST REGION Linear Technology Corporation 22141 Ventura Blvd. Suite 206 Woodland Hills, CA 91364 Phone: (818) 703-0835 FAX: (818) 703-0517 NORTHWEST REGION Linear Technology Corporation 782 Sycamore Dr. Milpitas, CA 95035 Phone: (408) 428-2050 FAX: (408) 432-6331
International Sales Offices
FRANCE Linear Technology S.A.R.L. Immeuble "Le Quartz" 58 Chemin de la Justice 92290 Chatenay Mallabry France Phone: 33-1-46316161 FAX: 33-1-46314613 GERMANY Linear Techonolgy GMBH Untere Hauptstr. 9 D-8057 Eching Germany Phone: 49-89-319741-0 FAX: 49-89-3194821 JAPAN Linear Technology KK 5F YZ Building 4-4-12 Iidabashi Chiyoda-Ku Tokyo, 102 Japan Phone: 81-3-3237-7891 FAX: 81-3-3237-8010 KOREA Linear Technology Korea Branch Namsong Building, #505 Itaewon-Dong 260-199 Yongsan-Ku, Seoul Korea Phone: 82-2-792-1617 FAX: 82-2-792-1619 SINGAPORE Linear Technology Pte. Ltd. 101 Boon Keng Road #02-15 Kallang Ind. Estates Singapore 1233 Phone: 65-293-5322 FAX: 65-292-0398 TAIWAN Linear Technology Corporation Rm. 801, No. 46, Sec. 2 Chung Shan N. Rd. Taipei, Taiwan, R.O.C. Phone: 886-2-521-7575 FAX: 886-2-562-2285
UNITED KINGDOM Linear Technology (UK) Ltd. The Coliseum, Riverside Way Camberley, Surrey GU15 3YL United Kingdom Phone: 44-276-677676 FAX: 44-276-64851
World Headquarters
Linear Technology Corporation 1630 McCarthy Blvd. Milpitas, CA 95035-7487 Phone: (408) 432-1900 FAX: (408) 434-0507
10/92
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7487
(408) 432-1900 q FAX: (408) 434-0507 q TELEX: 499-3977
LT/GP 1092 10K REV 0
(c) LINEAR TECHNOLOGY CORPORATION 1992

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